3D stacking: what it means.
Vertical die integration combines semiconductor dies in a stack. Depending on the implementation, bonding and vertical interconnect structures provide the electrical connections between layers. The arrangement is different from placing all the dies side by side. (Samsung: heterogeneous integration)
The term does not identify one universal interface or manufacturing process. HBM is a familiar stacked-memory example, while other integration schemes can stack different functions. Read which functions and layers the particular description covers. (Samsung: heterogeneous integration)
Put the definition to work.
“3D” describes an integration arrangement, not a universal interface. Consult the package description to understand which dies are stacked and how they connect. (Samsung: heterogeneous integration)
Questions to ask next.
Use these questions as a reading checklist, not as a device-selection recommendation. Exact manufacturer documentation takes priority over a general definition.
- Functions assigned to each layer
- Bonding and vertical interconnect method
- Thermal and integration documentation
For the broader explanation, explore chiplets and package integration. This page defines the term; the companion guide connects it to the rest of the system.
Common 3D stacking questions.
Are 3D stacking and chiplets synonyms?
No. Chiplet describes a functional die used in a larger system; stacking describes a physical arrangement. A chiplet-based system can use different package arrangements. (Samsung: heterogeneous integration)